1. Field of Invention
The present invention relates to a method for reducing memory consumption when carrying out Edge Enhancement in a multiple beam pixel apparatus. More particularly, the present invention relates to a method for reducing the consumption of hardware resources when carrying out multiple groups of Edge Enhancement operations.
2. Related Art
Recently, in the field of image processing, the key point of most research and development is to improve the visual effect of an image output apparatus (e.g. a printer) such that the visual effect generated after image output matches with the real subject. The edge of the original image object, e.g., texts, curves, three-dimensional objects, etc., can be approximated by the linear equation or natural logarithm, etc., to be more smooth. When these objects are digitally processed, they are required to be converted into a matrix form which is processable for an image output apparatus, and their edges are required to match the grids of the apparatus.
However, if the resolution of the image output apparatus is relatively low, the edge of the image object is found to be step-shaped of one grid by another grid through the naked eye, and a smooth edge as that of the original image object cannot be obtained. Therefore, various solutions are proposed to reduce the jagged effect on the edge of the image object, such that the image output by the image output apparatus can match with the real subject.
As for Edge Enhancement Method and Apparatus for Dot Matrix Devices disclosed in U.S. Pat. No. 5,029,108, the dotting state of the pixels of an image edge and that of the surrounding pixels are compared with a plurality of predetermined pictures, to determine which predetermined picture the pixels of the image edge match with, thus it is determined how to dot the pixels at the image edge to smooth the output image edge and to allow the image more accurately match with the original one. The enhancement of central pixels of each predetermined picture will be modified differently according to the dotting state of the surrounded pixels, for example, dotting at ¼ to the left of the central pixel, dotting at ⅔ to the right of the central pixels, etc.
Referring to FIG. 1, it is a structural schematic view of a conventional one beam Edge Enhancement Technology (EET) application. The serial data is read sequentially by an input unit 140 with the unit of one bit, and then after being processed by a one beam EET 10, the image is output to a display screen through a laser diode (LD) and a spinner, or printed by a printer, such that the edge of the output image is relatively smooth, without jagged edges.
Referring to FIG. 2, it is a schematic view of the operation of the conventional one beam EET 10. The serial data is stored in the fifth buffer of a first in first out (FIFO) buffer 120 after being read by an input unit 140, and a 9×5 table 110 can be taken out from the serial data in the FIFO buffer 120 through registering by a Static Random Access Memory (SRAM) 170. And the central pixel 130 of the table is detected to be a To Be Adjusted Pixel (TBAP) or not, and if it is, the TBAP is adjusted through the one beam EET 10.
Referring to FIG. 3, it is a structural schematic view of a conventional two-beam engine application. The serial data in FIG. 3 should be divided into odd column of serial data read by the first input unit 141, and even column of serial data read by the second input unit 142 sequentially, thus double speed can be achieved compared with the original one beam engine output. If the one beam EET 10 is further employed individually, the edge smoothness of the output image can be improved. Especially, since the EET carried out for the TBAP is at a slow speed, the output speed will be significantly improved, if double output speed is achieved.
However, in the Edge Enhancement operation, the serial data must be read in sequence, therefore the first input unit 141 and the second input unit 142 cannot be accessed at random. Instead, they must read the respective data to be processed respectively, thus a double sized FIFO buffer 120 and a SRAM 170 are required. This is equivalent to repeatedly reading data twice from the external, result in a mass consumption of the memory capacity used for operation in the internal of the system, especially the bandwidth used by the internal signal transmission bus, and the Central Processing Unit (CPU) resources consumed when transmitting data. No matter the Edge Enhancement is carried out to odd column of serial data or to even column of serial data, the data must be read repeatedly for many times to construct an individual 9×5 table 110. As a result, other processing procedures are significantly influenced. Although the printing speed is increased and output effects are improved, relative larger hardware costs are required, especially in the consumption of memory and CPU resources.